The present invention relates to a successive approximation type A/D converter, a method of controlling a successive approximation type A/D converter, a solid-state imaging device, and an imaging apparatus.
There is a type of A/D converters called successive approximation type A/D converters. In a successive approximation type A/D converter, comparison of magnitudes is repeated many times by a single comparator. More specifically, a voltage having amplitude that is one half of maximum amplitude (full scale; FS) is compared with an input voltage. The result of comparison obtained at this time corresponds to the most significant bit (MSB) of a digital value.
According to the value of the most significant bit, another comparison is subsequently carried out between the input voltage and a voltage FS/4 or 3FS/4 higher or lower than the first voltage by amplitude that is one half of the amplitude of the first voltage, i.e., amplitude equivalent to ¼FS. The result of comparison at this time constitutes the value of the next bit. The same step is repeated thereafter, and an A/D conversion process is completed by executing the step N times.
Known techniques for reducing the conversion time of a successive approximation A/D converter of this type include a technique involving the step of detecting upper bits which have been obtained at the same values at all of i cycles of preceding A/D conversion (i≧2) and applying the fixed values of those bits to the current cycle of successive approximation (for example, see JP-A-2006-108893 (Patent Document 1)).